发明名称 |
Computer systems, processes for turning a SRAM cell off, and processes for writing a SRAM cell and processes for reading data from a SRAM cell |
摘要 |
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.
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申请公布号 |
US6999351(B2) |
申请公布日期 |
2006.02.14 |
申请号 |
US20040820568 |
申请日期 |
2004.04.07 |
申请人 |
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发明人 |
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分类号 |
G11C7/00;G11C11/41;G11C11/412;G11C17/00;H01L21/8244;H01L27/11 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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地址 |
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