发明名称 Managing system and synchronization method for a plurality of VRM-type modules
摘要 A managing system manages a plurality of VRMs associated with a plurality of microprocessors and connected in parallel together between first and second voltage references, the VRMs having output terminals connected together and arranged to communicate over a common bus. The managing system includes an error amplifier being input an output voltage signal from the VRM plurality, a reference voltage, and a droop voltage produced through an equivalent droop resistor receiving an output current signal from the VRM plurality and being connected to the common bus. The error amplifier effects a comparison of the input signals to generate a control voltage signal to the VRM plurality. Advantageously, the managing system comprises a controller connected to the equivalent droop resistor.
申请公布号 US7000122(B2) 申请公布日期 2006.02.14
申请号 US20010982132 申请日期 2001.10.16
申请人 STMICROELECTRONICS S.R.L. 发明人 ZAFARANA ALESSANDRO;CASTELLI CLAUDIA
分类号 G06F1/26 主分类号 G06F1/26
代理机构 代理人
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