发明名称 Method and apparatus for reducing capacitive load-related power loss by gate charge adjustment
摘要 The present invention increases power efficiency in power FET applications with varying loads. A constant frequency mode can be used without detracting from efficiency. This is accomplished by reducing repetitive gate charge power losses. The present invention controls the channel impedance of the FET using a timed tri-state driver to drive a level of charge associated with the gate of the FET that is appropriate to the load requirements. When the voltage level at the FET gate reaches the appropriate level, the driver is tri-stated, so that the gate does not continue to charge.
申请公布号 US7000128(B1) 申请公布日期 2006.02.14
申请号 US20020334691 申请日期 2002.12.30
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 BROACH MICHAEL EUGENE
分类号 G06F1/26 主分类号 G06F1/26
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