发明名称 |
Method of fabricating integrated circuitry |
摘要 |
The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.
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申请公布号 |
US2006030144(A1) |
申请公布日期 |
2006.02.09 |
申请号 |
US20050209025 |
申请日期 |
2005.08.22 |
申请人 |
NEJAD HASAN;GREEN JAMES E |
发明人 |
NEJAD HASAN;GREEN JAMES E. |
分类号 |
H01L21/4763;H01L21/768;H01L23/522 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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