| 摘要 |
A number of techniques for implementing packet-buffering memory systems and packet-buffering memory architectures are disclosed. In one embodiment, a packet-buffering memory system comprises a high-latency memory sub system with a latency time of L and a low-latency memory subsystem. The low-latency memory subsystem contains enough memory to store an amount of packet data to last L seconds when accessed from low-latency memory subsystem at an access-rate of A. The packet-buffering system further comprises a FIFO controller that responds to a packet read request by simultaneously requesting packet data from said high-latency memory subsystem while simultaneously requesting and quickly responding with packet data obtained from the low-latency memory subsystem.
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