| 摘要 |
<P>PROBLEM TO BE SOLVED: To make it difficult to analyze a random number by further improving the irregularity of a random number train to be generated in a random number generation circuit using LFSR. <P>SOLUTION: The random number generation circuit comprises a counter 21 for obtaining an 8-bit count value by enabling the count of a clock signal CK1 and performing counting by a clock signal CK2, while the asynchronous clock signals CK1 and CK2 at a non-identical frequency are inputted to the counter section 21; count decoders 22-1 to 22-2 for decoding the 8-bit count value obtained by the counter section 21, and generating each of two types of random number disturbance signals EN1 and EN2; LFSRs 12-1, 12-2 in which the random number disturbance signals EN1 and EN2 are supplied as a latch enable, and the clock signal CK2 is supplied as a latch clock. The random number generation circuit further has an arithmetic section for generating a final random number train RAN3 by prescribed computation, based on the random number train, by generating random number trains RAN1, RAN2. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
