| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a single clock driven shift register in which the overlap phenomenon of output signals is solved. <P>SOLUTION: This shift register comprises a plurality of stage structures, wherein the M stage structure of the plurality of stage structures includes: a latch unit for latching the input signal of an M-1 stage structure based on a clock signal; a logic unit connected to the output terminal of the latch unit to apply logical operation to an output signal of the latch unit and the clock signal; and a non-overlap signal buffer connected to the output terminal of the logic unit and including at least three or more serially conncted inverters. In the non-overlap signal buffer, the output signal of the (odd-number)th inverter in a sequence coupled with the output terminal of the logic unit is fed in the latch unit of an M+1 stage structure, and the output signal of the non-overlap signal buffer of the M-1 stage structure is fed in the non-overlap signal buffer or the logic unit to delay the output signal of the non-overlap buffer. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
