发明名称 Single wire and three wire bus interoperability
摘要 Embodiments disclosed herein address the need for interoperability between existing serial bus interfaces and a single wire bus interface. In one aspect, the output or outputs of a three wire interface are selected in a first mode and the output of one or more single wire interfaces are selected in a second mode. In another aspect, a converter takes a single wire bus and produces signals according to a three wire interface. In yet another aspect, a termination symbol is inserted in a single wire interface signal, to facilitate conversion of the signal and connection to a three wire interface. In yet another aspect, a strobe signal and/or a clock signal are generated in response to a detected start symbol. In yet another aspect, a strobe signal is deasserted and/or a clock signal is deasserted in response to a detected termination symbol.
申请公布号 US2006031618(A1) 申请公布日期 2006.02.09
申请号 US20040851526 申请日期 2004.05.20
申请人 HANSQUINE DAVID W;MUNEER MUHAMMAD A 发明人 HANSQUINE DAVID W.;MUNEER MUHAMMAD A.
分类号 G06F13/14;G06F13/38;G06F13/42 主分类号 G06F13/14
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