发明名称 |
Method and apparatus for output data synchronization with system clock in DDR |
摘要 |
A method and apparatus for substantially reducing or eliminating the timing skew caused by delay elements in a delay locked loop. A method and apparatus is disclosed wherein a rising edge of a local timing signal is established and phase-locked to a rising edge of a system clock signal by delaying the system clock signal. A falling edge of the local timing signal is established and phase-locked to a falling edge of the system clock signal by further delaying only a portion of a signal representative of the delayed clock signal. By separately delaying different portions of the system clock signal and using the separately delayed portions to establish a local timing signal, a local timing signal may be established which is compensated for the varied effects of delay elements in a delay locked loop.
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申请公布号 |
US2006029173(A1) |
申请公布日期 |
2006.02.09 |
申请号 |
US20050247496 |
申请日期 |
2005.10.10 |
申请人 |
LI WEN;SCHOENFELD AARON M |
发明人 |
LI WEN;SCHOENFELD AARON M. |
分类号 |
H04L7/00;H03L7/081;H03L7/087;H03L7/107;H04L7/033;H04L25/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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