| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which stability can be improved without delaying an access time or without increasing a cell area. <P>SOLUTION: When a potential of a word line WL rises to a potential Vdd, an access transistor MAB is conducted, so that a memory node NB is connected to a bit line BLB. In the bit line BLB, a potential is reduced a little since a minus charge accumulated in a capacitor CB flows therein via the memory node NB. At such a time, the potential is not increased to a potential Vpp like conventional cases but the potential is kept at Vdd lower than Vpp for a predetermined period of time. Therefore, during said period of time, a gate voltage of the access transistor MAB becomes low and a value of current flowing to the access transistor MAB also becomes small in comparison with conventional cases, so that the increase in the potential of the memory node NB is reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
