| 摘要 |
<P>PROBLEM TO BE SOLVED: To contract a cache capacity without deteriorating performances in an application. <P>SOLUTION: A cacheable memory access space 210 receives memory access addresses differed in data structure from a processor 100 according to the using state of the cache capacity, and a cache hit detection part 230 determines whether data are hit or not based on a preset mode signal, an enbblk[n] signal, signals related to validity or invalidity of each way, a tag comparison address received from the cacheable space 210 and a tag received from a storage part 220. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
