| 摘要 |
A method of fabricating a semiconductor device includes an exposing process in which a lower pattern is formed by a first exposing process and an upper pattern is formed thereon by a second exposing process, wherein the exposure process includes the steps of obtaining a first correction value representing a difference of first and second alignment error correction parameter preset values respectively used at the time of a first exposing process of exposing the lower patterns in a current lot and in a just-before lot, obtaining, as a second correction value, an optimum correction amount of a third alignment error correction parameter preset value needed for proper alignment of the upper pattern in the second exposing process of the just-before lot, the third alignment error correction parameter has been used in the second exposing process of the just-before lot for exposing the upper pattern, and obtaining an optimum correction parameter prediction value to be used for exposing the upper pattern in the second exposing process of the current lot, from the first correction value and the second correction value.
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