| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device comprising an SRAM wherein a leak current is reduced. SOLUTION: In the SRAM comprising a storage unit wherein inputs/outputs of two inverter circuits are cross-connected, and a plurality of memory cells each comprised of a selection MOSFET provided between the storage unit and a complementary bit line and connecting its gate to a word line, a substrate bias switching circuit is provided. Thus, in the case of ordinary operation, a power supply voltage is supplied to an N-type well wherein a P-channel MOSFET of a memory cell is formed and a ground potential is supplied to a P-type well wherein an N-channel MOSFET is formed. During a standby state, a predetermined voltage which is smaller than the power supply voltage and in which a PN junction of the N-type well and a source of the P-channel MOSFET is not forwardly biased, is supplied to the N-type well and a predetermined voltage which is higher than the ground potential and in which a PN junction of the P-type well and a source of the N-channel MOSFET is not forwardly biased, is supplied to the P-type well. COPYRIGHT: (C)2006,JPO&NCIPI
|
