| 摘要 |
<P>PROBLEM TO BE SOLVED: To verify operation by executing an instruction retry function repeatedly as many times as needed. <P>SOLUTION: A parity generation circuit 202 inverts generated parity data such that a parity error is intentionally detected in a CSE entry at a completion determination to execute an instruction retry. If the request to execute the instruction retry will cause a program stop by an instruction retry mechanism, and if verification is canceled, a parity check circuit 205 for detecting a parity error assumes that no parity error has been detected to deter the execution of the instruction retry. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
