发明名称 |
Synchronous semiconductor memory device of fast random cycle system and test method thereof |
摘要 |
An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.
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申请公布号 |
US2006028885(A1) |
申请公布日期 |
2006.02.09 |
申请号 |
US20050244597 |
申请日期 |
2005.10.05 |
申请人 |
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发明人 |
INUZUKA KAZUKO;KAWAGUCHI KAZUAKI |
分类号 |
G01R31/30;G11C7/00;G01R31/28;G01R31/3185;G11C7/10;G11C7/22;G11C11/401;G11C11/407;G11C11/4076;G11C29/14;G11C29/46 |
主分类号 |
G01R31/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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