| 摘要 |
A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared ( 101 ). One of the faults is selected, and an initialization test pattern v 1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation ( 103 ), and a propagation test pattern v 2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation ( 105 ). A sequence formed by v 1 and v 2 is registered with a test pattern list ( 107 ), and the described operations are repeated until there remains no unprocessed fault in the fault list.
|
