发明名称 Coprocessor circuit architecture, for instance for digital encoding applications
摘要 A coprocessor circuit for processing image data in digital form, having a motion vector controller block for generating, starting from the image data, motion vector values that include predictor data and macroblock data relating to a current macroblock of the image data to be estimated and being adapted to be stored at respective memory addresses. Also included is an address generator block for extracting respective addresses from the motion vector values, a predictor fetch block for retrieving predictor data based on respective addresses extracted by the address generator block, a current macroblock fetch and distengine block for retrieving macroblock data based on respective addresses extracted by the address generator block and for processing the macroblock data according to a given function, and a decision block for collecting the retrieved data as partial results and selecting the best result therefrom.
申请公布号 US6996179(B2) 申请公布日期 2006.02.07
申请号 US20010819940 申请日期 2001.03.27
申请人 STMICROELECTRONICS S.R.L. 发明人 ROVATI FABRIZIO;PAU DANILO;PICCINELLI EMILIANO
分类号 H04N7/12;H04N7/26 主分类号 H04N7/12
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