| 摘要 |
An improved logic methodology that combines the speed advantages of dynamic logic with the low contention of static logic, such that the logic circuits are not adversely affected by high-leakage transistors. The logic circuit of the present invention comprises first and second stages, wherein first logic stage comprises clocked precharge and evaluate transistors and full-complementary low-beta-ratio static logic. Subsequent stages of the logic circuit comprise full-complementary low-beta-ratio static logic, wherein the logic devices in the subsequent stages are not connected to a clock signal. The low-beta-ratio static logic devices in said subsequent stage comprise pMOS transistors that are not connected to a contention keeper. Furthermore, the low-beta-ratio static logic transistors in the subsequent stage comprise pMOS transistors that are significantly smaller than pMOS devices found in normal static logic. The logic circuit of the present invention provides lower clock loading than traditional dynamic logic circuits due to the tapering of the transistor stacks in the subsequent stages and because the subsequent stages do not require a clock signal. Furthermore, the logic circuit of the present invention requires less area in the integrated circuit due to the reduced size of the pMOS transistors used in place of traditional contention keepers. The logic circuit of the present invention has a very low skew because the precharge is distributed across multiple pMOS devices.
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