发明名称 High-speed segmented data bus architecture
摘要 A system is provided for driving data signals in an integrated circuit device. The system includes a plurality of functional blocks, each having at least one input/output connection along one side of the integrated circuit device. A data bus comprises a plurality of electrically independent segments. Each segment of the data bus spans a respective portion of the one side of the integrated circuit device. A plurality of lines electrically couple the input/output connections of the functional blocks to the segments of the data bus. The lines are grouped into a plurality of subsets, and each subset is electrically coupled to a different segment of the data bus.
申请公布号 US6996652(B1) 申请公布日期 2006.02.07
申请号 US20020251530 申请日期 2002.09.19
申请人 INAPAC TECHNOLOGY, INC. 发明人 ONG ADRIAN E.
分类号 G06F13/14 主分类号 G06F13/14
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