| 摘要 |
A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected. |
