Apparatuses for a Clock Cycle Reducing of VLSI

摘要

A block matching estimation apparatus and a method thereof are disclosed. The block matching estimation apparatus includes a first predetermined number of first processor, each of which receives a search data at a rising edge of a clock, for calculating an absolute difference value between the search data and a reference data; and the first predetermined number of second processor, each of which receives a search data at a falling edge of the clock, for calculating an absolute difference value between the search data and a reference data, wherein the first processor and the second processor are alternately connected. The block matching estimator can decrease its the clock cycles by performing operations at the rising edge and the falling edge of the clock.