| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory access system for satisfying both transfer efficiency and responsibility without degrading its performance while a memory or the like is not individually prepared. SOLUTION: The memory access system comprises a DRAM interface section 70 having access to a memory such as a DRAM (Dynamic Random Access Memory) on the basis of a command controlling access to the memory from a master device such as a codec and a CPU (Central Processing Unit), and a selection section 50 selecting whether to preferentially output, to the DRAM interface section 70, the command for controlling access to the memory from the master device, for which responsibility is important, such as the CPU rather than the command for controlling access to the memory from the master device, for which transfer efficiency is important, such as the codec. COPYRIGHT: (C)2006,JPO&NCIPI
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