发明名称 CACHE MEMORY TEST SYSTEM, TEST METHOD AND TEST PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To provide a cache memory test system for performing the combined execution of cache coherence maintenance operations and the memory sequential property verification of access results by making a plurality of processors asynchronously perform continuous access to one and the same address and, one and the same cache line. <P>SOLUTION: This cache memory test system of a multi-processor system where a plurality of processors for storing cache are connected through a processor bus to a memory, is provided with a store instruction execution processor for continuously executing store instructions to the memory, a load instruction execution processor for continuously executing load instructions to the memory, an execution result comparing means for comparing whether or not the execution result of simultaneous access to the memory by each processor is matched with a predetermined expected value and a memory sequential property judging means for judging whether or not the memory sequential property is stored when it is judged that the execution results are matched as the comparison result. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006031156(A) 申请公布日期 2006.02.02
申请号 JP20040205840 申请日期 2004.07.13
申请人 FUJITSU LTD 发明人 WATANABE YUKI;MATSUMOTO NOBORU
分类号 G06F12/08;G06F12/16 主分类号 G06F12/08
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