发明名称 |
Techniques for reducing leakage current in memory devices |
摘要 |
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.
|
申请公布号 |
US2006023542(A1) |
申请公布日期 |
2006.02.02 |
申请号 |
US20040900246 |
申请日期 |
2004.07.27 |
申请人 |
DERNER SCOTT J;BRINGIVIJAYARAGHAVAN VENKATRAG;DIXIT ABHAY S;GRAHAM SCOT M;PORTER STEPHEN R;WILLIFORD ETHAN A |
发明人 |
DERNER SCOTT J.;BRINGIVIJAYARAGHAVAN VENKATRAGHAVAN;DIXIT ABHAY S.;GRAHAM SCOT M.;PORTER STEPHEN R.;WILLIFORD ETHAN A. |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|