| 摘要 |
A device for the regulated delay of a clock signal is proposed, which comprises a delay means in order to generate a delayed clock signal, and comparison means for the phase comparison of the delayed clock signal with a reference clock signal. The reference clock signal is in this connection preferably formed by the clock signal or is derived therefrom. On the basis of a comparison signal generated by the comparison means, a digital control signal is generated for controlling the delay means. The comparison means are configured so as to generate the comparison signal as a digitally coded signal that has a pulse duty ratio and a frequency that are determined by a further clock signal that is generated independently of the first clock signal, and that preferably has twice the frequency of the first clock signal.
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