| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock switching circuit capable of clock-switching in a fast timing without causing hazard. <P>SOLUTION: The clock switching circuit includes: a composite clock generating circuit 300 that receives a first clock CLK1, a second clock CLK2, a clock switching performance signal CES for switching between the clocks CLK1 and CLK2, fixes a level of the clock CLK2 to a second level and outputs the result as a clock switching composite clock CMP for a prescribed period including the leading edge or the trailing edge of the clock CLK1 when the signal CES is active for a period when the clock CLK2 is at a first level; a switching instruction signal generating circuit 200 that receives the clock CMP and the signal CES and outputs a clock switching instruction signal CDS; a clock selection signal generating circuit 100 that changes a level of a first clock selection signal CSS1 when the signal CDS is active; and a first selector 400 that selects either of the clock CLK1 or the clock CMP and outputs the selected clock in response to the level of the signal CSS1. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
