发明名称 DELAY TIME CALCULATION METHOD
摘要 PROBLEM TO BE SOLVED: To provide a delay time calculation method for calculating a delay time whose error is small in the delay time calculation of a logic circuit. SOLUTION: The operating characteristics of a transistor are expressed with the resistance element of a fixed value and a power supply voltage changing according to the lapse of a time. A power supply voltage is expressed with a waveform obtained by combining a straight line increasing from a fixed delay t0, and becoming V1 afterΔt1 and a straight line changing from V1 to E betweenΔt1 andΔt2, and becoming a fixed value E afterwards. The difference of the waveform shapes of an input waveform is received as a correction parameter, and the values ofΔt1, V1 andΔt2 are decided. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006031247(A) 申请公布日期 2006.02.02
申请号 JP20040207191 申请日期 2004.07.14
申请人 RENESAS TECHNOLOGY CORP 发明人 KOMOTA MICHIO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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