| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory and a control method of the semiconductor memory in which a probability of incurring a data read error can be decreased while preventing access time or circuit size from being increased even if transistor characteristics are varied in a single bit line type semiconductor memory which determines a read operation timing from the operation of a replica bit line. <P>SOLUTION: A gate length of a replica memory cell transistor is set longer than a gate length of a memory cell transistor, so that a distribution center mR of current driving ability distribution DR for replica memory cell transistors RM1-RMn is set to be lower than a distribution center mN of current driving ability distribution DN for memory cell transistors BM1-BMn, thereby reducing a probability for a lowering starting time of an ordinary data line DL to be delayed in comparison with a transmission timing of a latch control signal LCS. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
