RE-TIMER CIRCUIT FOR DATA RECOVERY WITH FAST RECOVERY FROM A LOW POWER MODE

摘要

Sampling and re-timing of data in a high speed communications interface between integrated circuits. Specifically, the sampling and re-timing of data where the receive circuit has a power down state and fast recovery from said low power state. The communications receiver with a plurality of receive channels and a phase locked loop, wherein each channel comprises a clock and data recovery circuit, and the phase locked loop generates an output clock distributed to all receive channels, so that each receive channel aligns the output clock from the phase locked loop to the receive data for the same receive channel.