| 摘要 |
A ferroelectric memory device characterized in comprising: a voltage source for generating a predetermined voltage; a first bit line and a second bit line; a first ferroelectric capacitor having one end electrically connected to the first bit line; a first resistance provided between the first bit line and the voltage source; a second ferroelectric capacitor having one end electrically connected to the second bit line; a second resistance provided between the second bit line and the voltage source; and a sense amplifier that judges data written in the first ferroelectric capacitor based on a potential on the first bit line, according to a timing at which a potential on the second bit line changes when the predetermined voltage is supplied to the first bit line and the second bit line.
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