发明名称 Multiple match detection circuit
摘要 Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR(x<SUB>i </SUB>AND x<SUB>j</SUB>), where x<SUB>i</SUB>=x<SUB>1</SUB>, x<SUB>2</SUB>, . . . , x<SUB>N-1</SUB>, x<SUB>j</SUB>epsilonx<SUB>i+1</SUB>, x<SUB>i+2</SUB>, . . . x<SUB>N</SUB>, and x<SUB>1</SUB>, x<SUB>2</SUB>, . . . , x<SUB>N </SUB>are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x<SUB>1 </SUB>OR x<SUB>2 </SUB>OR x<SUB>3 </SUB>OR . . . OR x<SUB>N</SUB>. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.
申请公布号 US2006023481(A1) 申请公布日期 2006.02.02
申请号 US20040909632 申请日期 2004.08.02
申请人 LSI LOGIC CORPORATION 发明人 SUN DECHANG
分类号 G11C15/00;G11C7/06 主分类号 G11C15/00
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