发明名称 REED-SOLOMON DECODING METHOD AND DEVICE
摘要 PROBLEM TO BE SOLVED: To calculate error values using a simple circuit configuration. SOLUTION: A Reed-Solomon decoding circuit comprises a syndrome generation circuit, an error position polynomial generating circuit, and an error value calculating circuit. The error value calculating circuit calculates a polynomial P(x), where the order of the coefficient of an error position polynomial is inverted (step S11); obtains a coefficientμij(i, j=0, 1, ..., k-1) of a polynomial Pi(x), obtained as a quotient when the polynomial P(x) is multiplied by (x-α<SP>^</SP>pi), (i=0, 1, ..., k-1) (step S12); successively multiplies the coefficientμij(i, j=0, 1, ..., k-1) by syndrome s(j¾j=0, 1, ..., 2t-1) for accumulative addition, divides a value obtained by the accumulative addition by Pi(xi), sets a value obtained by multiplication to an error value ei(i=0, 1, ..., k-1) at an error position pj(j=0, 1, ..., k-1)(step S13); and corrects an information series, based on the error value ei(i=0, 1, ..., k-1). COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006033233(A) 申请公布日期 2006.02.02
申请号 JP20040207023 申请日期 2004.07.14
申请人 SONY CORP 发明人 IDE NAOKI
分类号 H03M13/15;G06F11/08;G06F11/10;G11B20/10;G11B20/18 主分类号 H03M13/15
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