Embodiments of the invention provides a stepped tip junction region between a source/drain region of a transistor and a gate. In some embodiments, a spacer of the transistor includes a tip junction spacer layer and a source/drain spacer lacer.
申请公布号
WO2005117130(A3)
申请公布日期
2006.02.02
申请号
WO2005US14969
申请日期
2005.04.29
申请人
INTEL CORPORATION;BAN, IBRAHIM;SELL, BERNHARD;NATARAJAN, SANJAY;BOHR, MARK
发明人
BAN, IBRAHIM;SELL, BERNHARD;NATARAJAN, SANJAY;BOHR, MARK