| 摘要 |
PROBLEM TO BE SOLVED: To provide a novel cache controller by which an estimate for the worst execution time is facilitated and expected performance is achieved even for a program having low temporal/spacial locality. SOLUTION: The novel cache controller comprises: a CPU (Central Processing Unit) 1; a cache control section 211; a tag control section 201; data section 202; and a ROM (Read Only Memory) 13. The cache control section 21 controls: (A) no cache use; (B) cache use and replacement permission; and (C) cache use and no replacement permission by complying with process ID (Identification) executed by the CPU 1. When control information complying with the process ID falls in (A) or (B), the cache use is acceptable/unacceptable. In the case of (C), a command from a cache is sent to the CPU in a cache hit mode; and a command from the ROM is sent to the CPU in a mistake mode, provided that no cache replacement is done. COPYRIGHT: (C)2006,JPO&NCIPI
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