发明名称 Processor debugging apparatus and processor debugging method
摘要 A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
申请公布号 US2006026470(A1) 申请公布日期 2006.02.02
申请号 US20040986912 申请日期 2004.11.15
申请人 FUJITSU LIMITED 发明人 YAMASHITA HIDEO;KAN RYUJI
分类号 G01R31/28 主分类号 G01R31/28
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