| 摘要 |
An electronic device comprising a first processor and a second processor, the second processor coupled to the first processor and adapted to receive an address from the first processor, to pause execution of a first thread at a switch point, and to use the address to retrieve and execute a group of instructions in a second thread. Prior to executing the group of instructions in the second thread, the second processor pushes onto a hardware-controlled stack data pertaining to the switch point, the data comprising information needed to resume execution of the first thread at the switch point. |
