发明名称 Arithmetic unit and data processing unit
摘要 <p>For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.</p>
申请公布号 EP1622097(A2) 申请公布日期 2006.02.01
申请号 EP20050023307 申请日期 1998.12.01
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD 发明人 OHASHI, MASAHIRO;SAISHI, MANA;YONEZAWA, TOMONORI;KUROHMARU, SHUNICHI;KOUHASHI, HARUO;MATSUO, MASATOSHI;TOUJIMA, MASAYOSHI
分类号 G06F7/02;G06T9/00;G07F7/02;H03M7/40;H03M7/46 主分类号 G06F7/02
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