| 摘要 |
<p>A cacheable memory access space (210) receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector (230) determines whether data has been hit based on a mode signal, an enbblk [n] signal, and a signal indicating whether the way is valid or invalid, which are preset in the cache hit detector, a tag comparison address received from the cacheable memory access space (210), and a tag received from the storage unit (220).</p> |
