| 摘要 |
An integrated charge sensing scheme for sensing the resistance of a resistive memory (30) element is described. The current through a resistive memory cell (30) is used to charge a capacitor (75) coupled to a digit line. The voltage on the capacitor (75), which corresponds to the voltage on the digit line, is applied to one input of a comparator (40). When the voltage on the bit line exceeds a predetermined fixed voltage applied to the second input to thee comparator (40) less an offset, the comparator (40) switches logic state, charge is drawn off from the capacitor (75) and the capacitor (75) charges again. The process of charging and discharging the capacitor (75) occurs during a predetermined time period and the number of times the capacitor (75) switches during the time period represents the resistance of the memory element (30).
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