Multiplier circuit with offset compensation and quadricorrelator

摘要

A multiplier circuit has an analog multiplier with two signal inputs. A respective switching device is connected to each one of the two signal inputs of the analog multiplier for periodically reversing the polarity of the input voltages. A clock signal that can be fed to the switching devices has a changeover frequency that is preferably greater than or equal to twice the useful signal frequency. This suppresses offset-governed crosstalk of the input signals to the output of the analog multiplier. This principle can also be employed in quadricorrelators.