发明名称 ACCUMULATING TYPE ADDER
摘要 FIELD: computer science and engineering, possible use for constructing microprocessors and digital automation devices. ^ SUBSTANCE: adder has two RS-triggers, nine AND elements, five OR elements, NOT element, ten control buses. Adder performs operations of addition and subtraction, operations for bitwise shifting of code to left and right, inversion, two-module addition, logical addition and logical multiplication. ^ EFFECT: improved speed of operation, broadened list of arithmetic and logical operations possible to execute. ^ 2 cl, 1 dwg
申请公布号 RU2269153(C2) 申请公布日期 2006.01.27
申请号 RU20030134088 申请日期 2003.11.24
申请人 发明人 VLASOV BORIS MIKHAJLOVICH
分类号 G06F7/498;G06F7/50 主分类号 G06F7/498
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