发明名称 System and method for fully digital clock divider with non-integer divisor support
摘要 A system and method that use a first clock to digitally generate a second clock, wherein the ratio of the frequency of the first clock to the frequency of the second clock is a non-integer. Circuitry may be used to ensure that the first clock, or input clock, has a frequency at least equal to the highest of the desired output frequencies. The input clock may be used to generate several output clocks with different frequencies. If one of the output clocks has the same frequency as the input clock, the circuitry can be bypassed. The different clocks may be used to drive parts of a system, each of which may require a different frequency.
申请公布号 US2006017486(A1) 申请公布日期 2006.01.26
申请号 US20050135929 申请日期 2005.05.23
申请人 ILER JOHN 发明人 ILER JOHN
分类号 G06F1/04 主分类号 G06F1/04
代理机构 代理人
主权项
地址