发明名称 Flash memory device capable of reducing test time and test method thereof
摘要 A flash memory device includes a memory cell array arranged in rows and columns; a pad configured to be supplied with a high voltage from the exterior during a stress test operation; a column decoder configured to select a part of the columns in response to column selection signals; and a column predecoder configured to generate the column selection signals in response to an all column selection signal and a column address. The column predecoder simultaneously drives the column selection signals with the high voltage from the pad when the all column selection signal is activated during the stress test operation.
申请公布号 US2006018167(A1) 申请公布日期 2006.01.26
申请号 US20050232816 申请日期 2005.09.21
申请人 JEONG JAE-YONG;LIM HEUNG-SOO 发明人 JEONG JAE-YONG;LIM HEUNG-SOO
分类号 G11C16/06;G11C29/00;G11C8/12;G11C11/00;G11C16/02;G11C29/34;G11C29/56 主分类号 G11C16/06
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