发明名称 AUTOMATIC COMPRESSION/REDUCTION OF LATCH
摘要 PROBLEM TO BE SOLVED: To provide a method for designing an integrated circuit having latches. SOLUTION: The logic design of logic elements and latches is prepared and the logic elements and the latches are positioned within the integrated circuit according to the logic design in order to create a physical design. During the process of creating the physical design, the latches that do not transition into the same clock cycle, the latches unrelated to the same logic function, the latches within the same clock domain, and the latches in a given physical proximity to each other are combined in order to delete any redundant latches. This process of deleting the redundant latches includes replacing at least two of the latches by a single latch. The physical design is corrected through the process of deleting the redundant latches and a test is conducted on the corrected physical design to determine whether the corrected physical design will operate as expected. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006023859(A) 申请公布日期 2006.01.26
申请号 JP20040199833 申请日期 2004.07.06
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 SMITH JACK R;VENTRONE SEBASTIAN T
分类号 G06F17/50;H03K19/00 主分类号 G06F17/50
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