| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a computer system that can reduce power consumption by stably stopping the operation of a CPU that generates an operating clock in a built-in PLL circuit. <P>SOLUTION: When entering a power saving mode, the CPU 11 stops the built-in PLL circuit 16 with a software command. A clock detection circuit 14, upon detecting the output stop of a clock signal 22 from the CPU 11, outputs a supply stop signal 23, and a clock stop circuit 13 in turn stops the supply of a reference clock 21 to the CPU 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
