发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS TEST METHOD
摘要 PROBLEM TO BE SOLVED: To enhance the yield by reducing unnecessary failure judgment in the test of a semiconductor integrated circuit including an output buffer. SOLUTION: An auxiliary test arrangement (switching means 10, characteristics storage memory 11, correction voltage calculating means 12, limiter 13) for an output buffer by an LSI tester 30 is provided in an LSI 20. At first, the voltage/current characteristics of each output stage transistor (M1, M2) are measured and compared with characteristics stored in the characteristics storage memory 11 to check identity. If identity is not affirmed, the correction voltage calculating means 12 calculates an optimal input voltage level within a range not conflicting with the specification of the LSI 20 based on the difference between both characteristics. Reexamination is conducted based on the optimal input voltage level and an object judged defective unluckily is relieved. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006025100(A) 申请公布日期 2006.01.26
申请号 JP20040200527 申请日期 2004.07.07
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SATO AKIRA
分类号 H03K19/0175;G01R31/28;H01L21/822;H01L27/04;H03K19/00;H03K19/096 主分类号 H03K19/0175
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