发明名称
摘要 A method for testing the time delay error ratio ER of a device against a maximal allowable time delay error ratio ER<SUB>limit </SUB>with an early pass and/or early fail criterion, whereby the early pass and/or early fail criterion is allowed to be wrong only by a small probability D. ns time delays TD of the device are measured, thereby ne bad time delays of these ns time delays TD are detected. PD<SUB>high </SUB>and/or PD<SUB>low </SUB>are obtained, whereby PD<SUB>high </SUB>is the worst possible likelihood distribution and PD<SUB>low </SUB>is the best possible likelihood distribution containing the measured ne bad time delays with the probability D. The average numbers of erroneous bits NE<SUB>high </SUB>and NE<SUB>low </SUB>for PD<SUB>high </SUB>and PD<SUB>low </SUB>are obtained. NE<SUB>high </SUB>and NE<SUB>low </SUB>are compared with NE<SUB>limit</SUB>=ER<SUB>limit </SUB>ns. If NE<SUB>limit </SUB>is higher than NE<SUB>high </SUB>or NE<SUB>limit </SUB>is lower than NE<SUB>low </SUB>the test is stopped.
申请公布号 JP2006503461(A) 申请公布日期 2006.01.26
申请号 JP20040544053 申请日期 2003.10.01
申请人 发明人
分类号 H04B7/26;H04B1/707;H04B17/00;H04L1/24;H04Q7/34;H04Q7/38 主分类号 H04B7/26
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