Retention register with normal functionality independent of retention power supply

摘要

State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M 1 -M 3 ; M 1 -M 4 ) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a "don't care" signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N 10 ) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high V_t transistors (M 1 , M 2 , M 5 and M 6 ; M 3 , M 4 , M 5 and M 6 ) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.