发明名称 Method of manufacturing semiconductor device having damascene interconnection
摘要 In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1 . In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mAxsec/cm<SUP>2</SUP>.
申请公布号 US6989328(B2) 申请公布日期 2006.01.24
申请号 US20040777198 申请日期 2004.02.13
申请人 NEC ELECTRONICS CORPORATION 发明人 ARITA KOJI;MIKAGI KAORU;KITAO RYOHEI
分类号 C25D7/12;H01L21/44;H01L21/288;H01L21/3205;H01L21/768 主分类号 C25D7/12
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