发明名称 |
Apparatus and method for reducing power consumption by a data synchronizer |
摘要 |
An apparatus includes at least one logic storage unit which has a clock input. The apparatus also includes a logic circuit associated with the at least one logic storage unit. The logic circuit is capable of selectively preventing a clock signal from being applied to the clock input of the at least one logic storage unit.
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申请公布号 |
US6989695(B2) |
申请公布日期 |
2006.01.24 |
申请号 |
US20030454651 |
申请日期 |
2003.06.04 |
申请人 |
INTEL CORPORATION |
发明人 |
DIKE CHARLES E.;HAWKINS DAVID J. |
分类号 |
H03L7/00;G11C7/10;G11C7/22 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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